Template:Infobox CPU/testcases

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Testing sandbox version

{{Infobox CPU/sandbox}}

MOS Technology 6502
MOS 6502AD 4585 top.jpg
A MOS 6502 processor in a DIP-40 plastic package. The four-digit date code indicates it was made in the 45th week of 1985
ProducedTemplate:Start date and age
Common manufacturer(s)
Max. CPU clock rate1 MHz to 2 MHz
Instruction setMOS 6502
Instructions56
Data width8
Address width16
Package(s)
Template:PAGENAMEBASE
KL Intel i286.jpg
An 8MHz Intel 80286 Microprocessor
ProducedFrom 1982 to early 1990s
Common manufacturer(s)
Max. CPU clock rate6 MHz (4 MHz for a short time) to 25 MHz
Instruction setx86-16 (with MMU)
Model80286 Series
PredecessorIntel 80186
SuccessorIntel 80386
Co-processorIntel 80287
Package(s)
P5
L1 cache16 KB to 32 KB
ModelPentium Series
CreatedMarch 22, 1993
ArchitectureP5 x86 (IA-32)
InstructionsMMX
Socket(s)
PredecessorIntel 80486
SuccessorP6
P6
L1 cache32 KB
L2 cache128 KB to 512 KB
256 KB to 2048 KB (Xeon)
ModelCeleron Series
CreatedNovember 1, 1995
Transistors7.5M 350 nm
ArchitectureP6 x86
InstructionsMMX
Extensions
Socket(s)
PredecessorP5
SuccessorNetBurst
VariantPentium M
P6 Pentium M
L1 cache32KB
L2 cache512 KB to 2048 KB
ModelA100 Series
Created2004
Transistors77M 130 nm (B1, B2)
ArchitectureP6 x86
InstructionsMMX
Extensions
SocketSocket M
PredecessorP5
SuccessorEnhanced Pentium M
P6 Enhanced Pentium M
L1 cache32 KB
L2 cache1 MB to 2 MB
2 MB (Xeon)
ModelCeleron M Series
Created2006
Transistors151M 65 nm (C0, D0)
ArchitectureP6 x86
InstructionsMMX
Extensions
SocketSocket M
PredecessorPentium M
SuccessorIntel Core
NetBurst
L1 cache8 KB to 16 KB per core
L2 cache128 KB to 2048 KB
256 KB to 2048 KB (Xeon)
L3 cache4 MB to 16 MB shared
ModelCeleron Series
CreatedNovember 20, 2000
Transistors42M 180 nm (B2, C1, D0, E0)
ArchitectureNetBurst x86
InstructionsMMX
Extensions
Socket(s)
PredecessorP6
SuccessorIntel Core
Intel Core
L1 cache64 KB per core
L2 cache1 MB to 8 MB unified
L3 cache8 MB to 16 MB shared (Xeon)
ModelCeleron Series
Created2006
Transistors105M 65 nm (A1, M0)
ArchitectureIntel Core x86
InstructionsMMX
Extensions
Socket(s)
PredecessorNetBurst
SuccessorPenryn (tick)
Nehalem (tock)
Penryn
L1 cache64 KB per core
L2 cache3 MB to 12 MB unified
L3 cache8 MB to 16 MB shared (Xeon)
ModelCeleron Series
Created2007-2008
Transistors228M 45 nm (R0)
ArchitectureIntel Core x86
InstructionsMMX
Extensions
Socket(s)
PredecessorIntel Core
SuccessorNehalem
Nehalem
L1 cache64KB per core
L2 cache256KB per core
L3 cache4MB to 12MB shared
ModelCeleron Series
CreatedNovember 2008
Transistors731M 45 nm (C0, D0)
ArchitectureNehalem x86
InstructionsMMX
Extensions
Socket(s)
PredecessorIntel Core (tock)
Penryn (tick)
SuccessorWestmere (tick)
Sandy Bridge (tock)
Westmere
L1 cache64KB per core
L2 cache256KB per core
L3 cache4MB to 30MB shared
ModelCeleron Series
CreatedJanuary 7, 2010
Transistors382M 32nm (C2)
ArchitectureNehalem x86
InstructionsMMX, AES-NI, CLMUL
Extensions
Socket(s)
PredecessorNehalem
SuccessorSandy Bridge
GPU533 MHz to 900 MHz
177M 45nm (K0)
Sandy Bridge
L1 cache64KB per core
L2 cache256KB per core
L3 cache3MB to 8MB shared
10MB to 15MB (Extreme)
3MB to 20MB (Xeon)
ModelCeleron Series
CreatedJanuary 2011
Transistors504M 32nm (Q0)
ArchitectureSandy Bridge x86
InstructionsMMX, AES-NI, CLMUL
Extensions
Socket(s)
PredecessorNehalem (tock)
Westmere (tick)
SuccessorIvy Bridge (tick)
Haswell (tock)
GPUHD Graphics 2000
650 MHz to 1250 MHz
Ivy Bridge
CPUID code0306A9h
Product code80637 (desktop)
L1 cache64KB per core
L2 cache256KB per core
L3 cache3MB to 8MB shared
ModelPentium G Series
CreatedApril 29, 2012
Transistors624M 22nm (L1)
ArchitectureSandy Bridge x86
InstructionsMMX, AES-NI, CLMUL
Extensions
Socket(s)
PredecessorSandy Bridge
SuccessorHaswell
GPUHD Graphics 2500
650 MHz to 1150 MHz
Haswell
ModelCore i3 Series
Created2013
Transistors22 nm transistors
Last level cache35MB
ArchitectureHaswell x86
InstructionsMMX, AES-NI, CLMUL, FMA3
Extensions
Socket(s)
PredecessorSandy Bridge (tock)
SuccessorBroadwell (tick)
Broadwell
ModelCore i3 Series
Core i5 Series
Core i7 Series
Created2014
Transistors14 nm transistors
Last level cache35MB
ArchitectureHaswell x86
InstructionsMMX, AES-NI, CLMUL, FMA3
Extensions
PredecessorHaswell
SuccessorSkylake
Skylake
ModelCore i3 Series
Core i5 Series
Core i7 Series
Createdexpected 2015-2016
Transistors14 nm transistors
ArchitectureSkylake x86
InstructionsMMX, AES-NI, CLMUL, FMA3
Extensions
PredecessorHaswell (tock)
Broadwell (tick)
SuccessorCannonlake (tick)
Cannonlake
ModelCore i3 Series
Core i5 Series
Core i7 Series
Created2016
Transistors10 nm transistors
ArchitectureSkylake x86
InstructionsMMX, AES-NI, CLMUL, FMA3
Extensions
PredecessorSkylake
Apple A11 Bionic
Apple A11.jpg
ProducedFrom September 12, 2017 to present
Designed byApple Inc.
Common manufacturer(s)
Max. CPU clock rateto 2.39 GHz 
Min. feature size10 nm
Instruction setA64
MicroarchitectureARMv8‑A compatible
Product codeAPL1W72
Cores6
Core name(s)
  • Monsoon
  • Mistral
L1 cache32 KB instruction, 32 KB data
L2 cache8 MB
L3 cachenone
PredecessorApple A10 Fusion
GPUApple-designed 3 core
ApplicationMobile
Product code name(s)
  • test1

Testing main template

{{Infobox CPU}}

Template:PAGENAMEBASE
KL Intel i286.jpg
An 8MHz Intel 80286 Microprocessor
General information
Launched1982
Discontinuedearly 1990s
Common manufacturer(s)
Performance
Max. CPU clock rate6 MHz (4 MHz for a short time) to 25 MHz
FSB speeds6 MHz to 25 MHz
Architecture and classification
Instruction setx86-16 (with MMU)
Physical specifications
Co-processorIntel 80287
Package(s)
Products, models, variants
Model(s)
  • 80286 Series
History
PredecessorIntel 80186
SuccessorIntel 80386
P5
General information
LaunchedMarch 22, 1993
Performance
Max. CPU clock rate60 MHz to 300 MHz
FSB speeds50 MHz to 66 MHz
Cache
L1 cache16 KB to 32 KB
Architecture and classification
ArchitectureP5 x86 (IA-32)
InstructionsMMX
Physical specifications
Socket(s)
Products, models, variants
Model(s)
  • Pentium Series
  • Pentium OverDrive Series
  • Pentium MMX Series
History
PredecessorIntel 80486
SuccessorP6
P6
General information
LaunchedNovember 1, 1995
Performance
Max. CPU clock rate233 MHz to 1.40 GHz
FSB speeds66 MHz to 133 MHz
Cache
L1 cache32 KB
L2 cache128 KB to 512 KB
256 KB to 2048 KB (Xeon)
Architecture and classification
ArchitectureP6 x86
InstructionsMMX
Extensions
Physical specifications
Transistors
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
  • Pentium II Series
  • Pentium III Series
  • Pentium Pro Series
  • Pentium II Xeon Series
  • Pentium III Xeon Series
Variant(s)Pentium M
History
PredecessorP5
SuccessorNetBurst
P6 Pentium M
General information
Launched2004
Performance
Max. CPU clock rate600 MHz to 2.26 GHz
FSB speeds400 MHz to 533 MHz
Cache
L1 cache32KB
L2 cache512 KB to 2048 KB
Architecture and classification
ArchitectureP6 x86
InstructionsMMX
Extensions
Physical specifications
Transistors
Socket(s)
Products, models, variants
Model(s)
  • A100 Series
  • EP80579 Series
  • Celeron M Series
  • Pentium M Series
History
PredecessorP5
SuccessorEnhanced Pentium M
P6 Enhanced Pentium M
General information
Launched2006
Performance
Max. CPU clock rate1.06 GHz to 2.33 GHz
FSB speeds533 MHz to 667 MHz
Cache
L1 cache32 KB
L2 cache1 MB to 2 MB
2 MB (Xeon)
Architecture and classification
ArchitectureP6 x86
InstructionsMMX
Extensions
Physical specifications
Transistors
Socket(s)
Products, models, variants
Model(s)
  • Celeron M Series
  • Pentium Dual-Core Series
  • Core Solo Series
  • Core Duo Series
  • Xeon LV Series
History
PredecessorPentium M
SuccessorIntel Core
NetBurst
General information
LaunchedNovember 20, 2000
Performance
Max. CPU clock rate267 MHz to 3.73 GHz
FSB speeds400 MT/s to 1066 MT/s
Cache
L1 cache8 KB to 16 KB per core
L2 cache128 KB to 2048 KB
256 KB to 2048 KB (Xeon)
L3 cache4 MB to 16 MB shared
Architecture and classification
ArchitectureNetBurst x86
InstructionsMMX
Extensions
Physical specifications
Transistors
Cores
  • 1-2 (2-4)
  • 2-6 (2-6) (Xeon)
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
  • Celeron D Series
  • Pentium 4 Series
  • Pentium D Series
  • Xeon Series
History
PredecessorP6
SuccessorIntel Core
Intel Core
General information
Launched2006
Performance
Max. CPU clock rate1.06 GHz to 3.33 GHz
FSB speeds533 MT/s to 1600 MT/s
Cache
L1 cache64 KB per core
L2 cache1 MB to 8 MB unified
L3 cache8 MB to 16 MB shared (Xeon)
Architecture and classification
ArchitectureIntel Core x86
InstructionsMMX
Extensions
Physical specifications
Transistors
Cores
  • 1-4 (1-4)
  • 2-6 (2-6) (Xeon)
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
  • Pentium Series
  • Pentium Dual-Core Series
  • Core 2 Solo Series
  • Core 2 Duo Series
  • Core 2 Quad Series
  • Core 2 Extreme Series
  • Xeon Series
History
PredecessorNetBurst
SuccessorPenryn (tick)
Nehalem (tock)
Penryn
General information
Launched2007-2008
Performance
Max. CPU clock rate1.06 GHz to 3.33 GHz
FSB speeds533 MT/s to 1600 MT/s
Cache
L1 cache64 KB per core
L2 cache3 MB to 12 MB unified
L3 cache8 MB to 16 MB shared (Xeon)
Architecture and classification
ArchitectureIntel Core x86
InstructionsMMX
Extensions
Physical specifications
Transistors
Cores
  • 1-4 (1-4)
  • 2-6 (2-6) (Xeon)
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
  • Pentium Series
  • Pentium Dual-Core Series
  • Core 2 Solo Series
  • Core 2 Duo Series
  • Core 2 Quad Series
  • Core 2 Extreme Series
  • Xeon Series
History
PredecessorIntel Core
SuccessorNehalem
Nehalem
General information
LaunchedNovember 2008
Performance
Max. CPU clock rate1.06 GHz to 3.33 GHz
Cache
L1 cache64KB per core
L2 cache256KB per core
L3 cache4MB to 12MB shared
Architecture and classification
ArchitectureNehalem x86
InstructionsMMX
Extensions
Physical specifications
Transistors
Cores
  • 2-6 (2-12)
  • 6 (12) (Extreme)
  • 4-8 (4-16) (Xeon)
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
  • Pentium Series
  • Core i3 Series
  • Core i5 Series
  • Core i7 Series
  • Core i7 Extreme Series
  • Xeon Series
History
PredecessorIntel Core (tock)
Penryn (tick)
SuccessorWestmere (tick)
Sandy Bridge (tock)
Westmere
General information
LaunchedJanuary 7, 2010
Performance
Max. CPU clock rate1.06 GHz to 3.46 GHz
Cache
L1 cache64KB per core
L2 cache256KB per core
L3 cache4MB to 30MB shared
Architecture and classification
ArchitectureNehalem x86
InstructionsMMX, AES-NI, CLMUL
Extensions
Physical specifications
Transistors
Cores
  • 2-6 (2-12)
  • 6 (12) (Extreme)
  • 4-10 (4-20) (Xeon)
GPU(s)533 MHz to 900 MHz
177M 45nm (K0)
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
  • Pentium Series
  • Core i3 Series
  • Core i5 Series
  • Core i7 Series
  • Core i7 Extreme Series
  • Xeon Series
History
PredecessorNehalem
SuccessorSandy Bridge
Sandy Bridge
General information
LaunchedJanuary 2011
Performance
Max. CPU clock rate1.60 GHz to 3.60 GHz
Cache
L1 cache64KB per core
L2 cache256KB per core
L3 cache3MB to 8MB shared
10MB to 15MB (Extreme)
3MB to 20MB (Xeon)
Architecture and classification
ArchitectureSandy Bridge x86
InstructionsMMX, AES-NI, CLMUL
Extensions
Physical specifications
Transistors
Cores
  • 1-4 (2-8)
  • 4-6 (8-12) (Extreme)
  • 2-8 (4-16) (Xeon)
GPU(s)HD Graphics 2000
650 MHz to 1250 MHz
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
  • Pentium Series
  • Core i3 Series
  • Core i5 Series
  • Core i7 Series
  • Core i7 Extreme Series
  • Xeon E3 Series
  • Xeon E5 Series
History
PredecessorNehalem (tock)
Westmere (tick)
SuccessorIvy Bridge (tick)
Haswell (tock)

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