Template:AMD x86 CPU features

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The following table shows features of AMD's CPUs Template:When pagename is

Template:Rh rowspan="12" | Codename Template:Rh rowspan="3" | Server Template:Rh | High-end SledgeHammer Athens Egypt Santa Rosa Barcelona Shanghai Istanbul Magny-Cours Interlagos Abu Dhabi
Template:Rh | Mainstream Palomino Thoroughbred Barton SledgeHammer Troy Italy Santa Rosa Barcelona Shanghai Istanbul Lisbon Valencia Seoul Naples Rome
Template:Rh | Entry SledgeHammer Venus,
Venus
Denmark Santa Ana Budapest Suzuka Zurich Delhi
Template:Rh rowspan="4" | Desktop Template:Rh | High-end SledgeHammer Windsor Whitehaven Colfax Castle Peak
Template:Rh | Mainstream Am386 Am486 Am5x86 SSA/5 5k86 K6 Model 6 Little Foot Chomper Extended,
Chomper
Sharptooth Argon Orion,
Pluto
Thunderbird,
Spitfire
Palomino,
Morgan
Thoroughbred,
Applebred,
Thoroughbred-B
Barton,
Thorton,
Barton,
Thorton
ClawHammer,
ClawHammer,
Newcastle
Winchester San Diego,
San Diego,
Venice,
Palermo
Toledo,
Manchester, Toledo,
Manchester, Toledo
Manila, Manila Windsor,
Windsor,
Orleans
Brisbane,
Lima,
Brisbane,
Sparta
Agena, Toliman,
Kuma
Deneb, TWKR, Propus, Heka, Callisto, Regor,
Propus, Rana, Regor, Sargas,
Regor, Sargas
Thuban, Zosma,
Zosma
Zambezi Vishera Summit Ridge Pinnacle Ridge Matisse Vermeer
Template:Rh | Entry ClawHammer,
Newcastle,
Paris
Palermo Venice,
Palermo
Template:Rh | Basic GX[lower-alpha 1] GXi[lower-alpha 1] GXm[lower-alpha 2]
Template:Rh rowspan=4 | Mobile Template:Rh | Performance Thoroughbred Barton ClawHammer Newark Champlain,
Champlain
Template:Rh | Mainstream K6-III-P K6-III+,
K6-2+
Corvette Thoroughbred,
Thoroughbred
Barton Odessa Oakville Lancaster Trinidad,
Taylor,
Richmond
Lion,
Tyler,
Tyler
Caspian,
Caspian
Champlain,
Champlain,
Geneva
Template:Rh | Entry Spitfire Camaro Applebred Dublin,
Dublin,
Dublin
Georgetown,
Sonora
Albany,
Roma
Keene Sable,
Sable,
Conesus,
Sherman,
Huron
Caspian Champlain,
Geneva
Template:Rh | Basic Caspian Geneva GX[lower-alpha 1] GXi[lower-alpha 1] GXm[lower-alpha 2] GXLV[lower-alpha 3] GX1 SC GX2[lower-alpha 4] LX NX
Template:Rh colspan=2 | Embedded Champlain,
Geneva
Snowy Owl
Template:Rh colspan="3" | Platform High, standard, and low power Low and ultra-low power
Template:Rh colspan="3" | IGP N/A colspan="8" Template:Ya N/A
Template:Rh colspan="3" | Released March 1991 April 1993 November 1995 March 1996 October 1996 April 1997 January 1998 May 1998 February 1999 April 2000 June 1999 November 1999 June 2000 October 2001 June 2002 February 2003 September 2003 August 2004 April 2005 May 2005 May 2006 December 2006 September 2007 November 2008 June 2009 March 2010 October 2011 October 2012 March 2017 April 2018 July 2019 November 2020 February 1997 1997 1998 1999 April 2000 September 2000 June 2002 May 2005 May 2004
Template:Rh colspan="3" | CPU microarchitecture Am386 Am486 Am5x86 SSA/5 5k86 K6 K6-2 K6-III K6-III+ K7 K8 K10 Bulldozer Piledriver Zen Zen+ Zen 2 Zen 3 MediaGX Thoroughbred
Template:Rh colspan="3" | ISA x86-32 x86-32, x86-64 x86-64 x86-32
Template:Rh rowspan="10" | Socket Template:Rh rowspan=5 | Server Template:Rh | High-end N/A 940 N/A 940 N/A F N/A F F+ G34 N/A N/A
Template:Rh | Mainstream N/A A C32 SP3
Template:Rh | Entry N/A 939 940, 939 AM2 AM2+ AM3, F+ N/A AM3+
Template:Rh | Basic N/A
Template:Rh | Micro
Template:Rh rowspan="4" | Desktop Template:Rh | High-end N/A 940 N/A 1207 FX N/A TR4 sTRX4
Template:Rh | Mainstream 1, 2, 3 5, 7 7 Super 7 N/A Slot A Slot A, A A 939 AM2 AM2+ AM2+, AM3 N/A AM3+ AM4
Template:Rh | Entry N/A 754 N/A
Template:Rh | Basic N/A N/A
Template:Rh colspan=2 | Other Super 7 A A, 563 754 N/A S1 S1, ASB2 N/A SP4 A
Template:Rh colspan="3" | PCI Express version N/A 1.1, 2.0 2.0 3.0 4.0
Template:Rh colspan="3" | Fab. (nm) AMD 1500
(bulk)
AMD 800
(bulk)
AMD 700
(bulk)
AMD 500
(bulk))
AMD 350
(bulk)
AMD 350
(bulk)
AMD 500
(bulk)
AMD 350
(bulk)
AMD 350
(bulk)
AMD 250
(bulk)
AMD 180
(bulk)
AMD 250
(bulk)
AMD 180
(bulk)
AMD 130
(SOI)
AMD 90
(SOI)
AMD, GF 65
(strained SOI)
AMD, GF 45
(strained SOI)
GF 45
(strained SOI)
GF 32SHP
(HKMG SOI)
GF 14LPP
(FinFET bulk)
GF 12LP
(FinFET bulk)
TSMC N7
(FinFET bulk)
IBM 400
(bulk)
IBM 350
(bulk)
IBM, NS 350
(bulk)
NS 250
(bulk)
NS 180
(bulk)
TSMC 150
(bulk)
TSMC 130
(bulk)
AMD 130
(SOI)
Template:Rh colspan="3" | die area (mm2)
Template:Rh colspan="3" | Min TDP 0.32
Template:Rh colspan="3" | Max TDP 3.03 50 65 72 79.2 104 67 104 110 62 125 89 125 137 140 220 180 250 280 105 2.5 1.2 0.9 3.9
Template:Rh colspan="3" | Max stock base clock (GHz) 0.04 0.12 0.16 0.1 0.133 0.233 0.3 0.55 0.475 0.55 0.7 1 1.4 1.733 2.2 2.333 2.6 2.2 3 2.8 2.2 3.2 3.1 2.6 3.7 2.8 3.9 4.7 3.8 3.7 3.9 3.8 0.15 0.18 0.3 0.266 0.33 0.3 0.4 0.6 1.8
Template:Rh colspan="3" | Max CPUs per node[lower-alpha 5] 1 2 8 1 8 1 8 1 8 4 2 1 1
Template:Rh colspan="3" | Max cores per CPU 1 2 4 6 12 16 32 64 16 1
Template:Rh colspan="3" | Max threads per core 1 2 1
Template:Rh colspan="3" | Integer structure 2+2 2+1+1 3+3 2+2 4+2 4+2+1 1+1 3+3
Template:Rh colspan="3" | Basic architecture level i386 i486 i586 pentium-mmx PREFETCHW PREFETCHW and i686[lower-alpha 6] PAE NX bit 64-bit LAHF/SAHF[lower-alpha 7] CMPXCHG16B AMD-V[lower-alpha 8] RVI and ABM IOMMU[lower-alpha 9] IOMMU[lower-alpha 10], BMI1, AES-NI, CLMUL and F16C i586 CMOV CMOV and PREFETCHW PAE
Template:Rh colspan="3" | TBM N/A Template:Ya N/A
Template:Rh colspan="3" | AVIC, BMI2, MOVBE, ADX, SHA, RDRAND/RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO N/A colspan="4" Template:Ya
Template:Rh colspan="3" | x2APIC, WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT N/A colspan="2" Template:Ya
Template:Rh colspan="3" | FPUs per core 0 0, 1 1 0.5 1 1
Template:Rh colspan="3" | Pipes per FPU 1 2 1 2
Template:Rh colspan="3" | FPU pipe width 80-bit 80-bit, 128-bit 128-bit 256-bit 80-bit
Template:Rh colspan="3" | CPU instruction set SIMD level colspan=5 Template:N/A MMX 3DNow! 3DNow!+ Enhanced 3DNow! SSE SSE2 SSE3 SSE4a[lower-alpha 11] AVX AVX2 N/A MMX Inverse 3DNow! SSE
Template:Rh colspan="3" | 3DNow! N/A 3DNow! 3DNow!+ N/A N/A Inverse 3DNow! 3DNow!+
Template:Rh colspan="3" | PREFETCH/PREFETCHW N/A colspan="26" Template:Ya N/A colspan=3 Template:Ya
Template:Rh colspan="3" | FMA4, LWP, and XOP N/A colspan="2" Template:Ya N/A N/A
Template:Rh colspan="3" | FMA3 N/A colspan="5" Template:Ya
Template:Rh colspan="3" | Max total L1 cache (KiB) 16 24 64 128 256 128 256 512 768 1536 768 3072 4096 1024 16 128
Template:Rh colspan="3" | L2 caches per core 0, 1 (board) 1 0.5 1 1
Template:Rh colspan="3" | Max total L2 cache (MiB) 2 (board) 0.25 0.5 0.25 0.5 1 0.5 1 2 0.5 2 1 2 3 6 16 32 8 0.125 0.25
Template:Rh colspan="3" | L2 cache associativity (ways) 4 2 16 8 4 16
Template:Rh colspan="3" | Max total L3 cache (MiB) N/A 2 (board) N/A 2 6 12 16 64 256 64 N/A
Template:Rh colspan="3" | L3 cache associativity (ways) 32 48 64 16
Template:Rh colspan="3" | L3 cache scheme victim
Template:Rh colspan="3" | Max stock DRAM support SDR DDR DDR-400 DDR2-800 DDR2-1066 DDR2-1066, DDR3-1333 DDR3-1866 DDR4-2666 DDR4-2933 DDR4-3200 EDO SDR-111 SDR-133, DDR-233 DDR-400
Template:Rh colspan="3" | Max DRAM channels per CPU 1 2 4 8 4 8 2
Template:Rh colspan="3" | Max stock DRAM bandwidth (GB/s) per CPU 6.4 12.8 17.056 21.328 42.656 51.2 59.712 170.624 93.856 204.8 51.2

Template:Noteslist

Template documentation

References


See also


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