imported>YantarCoast |
imported>TheImaCow |
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− | {{Navbox | + | {{Sandbox notice}} |
− | |state={{{state|autocollapse}}}
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− | |name=Intel processor roadmap
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− | |title=Intel CPU core roadmaps from [[P6 (microarchitecture)|P6]] to [[Alder Lake (microarchitecture)|Alder Lake]]
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− | |list1=<noinclude>{{Cleanup section|reason=When from ''Bonnell'' to ''Silvermont'' is [[Tick–tock model#Atom roadmap|just a Tick]] (die shrink) than ''Silvermont'' is part of ''Bonnell'' and not a unique microarchitecture? |date=October 2019}}</noinclude>
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− | <table class="wikitable" style="border:none; text-align:center;">
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− | <tr>
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− | <th colspan="2" style="background-color:#E6E6FF">[[Intel Atom|Atom (ULV)]]</th>
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− | <td rowspan="34" style="background-color:white; border:none;"></td>
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− | <th rowspan="2">Feature size</th>
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− | <td rowspan="34" style="background-color:white; border:none;"></td>
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− | <th colspan="2" style="background-color:#E6E6FF">[[X86|x86]]</th>
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− | <td colspan="6" rowspan="7" style="background-color:white; border:none;"></td>
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− | </tr>
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− | <tr>
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− | <th style="background-color:#E6E6FF">[[Microarchitecture|Microarchi.]]</th>
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− | <th style="background-color:#E6E6FF">Step</th>
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− | <th style="background-color:#E6E6FF">[[Microarchitecture|Microarchi.]]</th>
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− | <th style="background-color:#E6E6FF">Step</th>
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− | </tr>
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− | <tr>
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− | <td colspan="2" rowspan="13"></td>
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− | <th>[[600 nanometer|600 nm]]</th>
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− | <td rowspan="12"><b>[[P6 (microarchitecture)|P6]]</b></td>
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− | <td>[[Pentium Pro]]<br>(133 MHz)</td>
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− | </tr>
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− | <tr>
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− | <th>[[500 nanometer|500 nm]]</th>
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− | <td>[[Pentium Pro]]<br>(150 MHz)</td>
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− | </tr>
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− | <tr>
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− | <th rowspan="2">[[350 nanometer|350 nm]]</th>
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− | <td>[[Pentium Pro]]<br>(166–200 MHz)</td>
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− | </tr>
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− | <tr>
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− | <td>[[Klamath (microprocessor)|Klamath]]</td>
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− | </tr>
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− | <tr>
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− | <th rowspan="2">[[250 nanometer|250 nm]]</th>
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− | <td>[[Deschutes (microprocessor)|Deschutes]]</td>
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− | </tr>
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− | <tr>
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− | <td>[[Katmai (microprocessor)|Katmai]]</td>
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− | <td rowspan="7" style="background-color:white; border:none;"></td>
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− | <th style="background-color:#E6E6FF">[[NetBurst|NetBurst]]</th>
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− | <td colspan="4" rowspan="3" style="background-color:white; border:none;"></td>
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− | </tr>
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− | <tr>
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− | <th>[[180 nanometer|180 nm]]</th>
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− | <td>[[Coppermine (microprocessor)|Coppermine]]</td>
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− | <td>[[Pentium 4#Willamette|Willamette]]</td>
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− | </tr>
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− | <tr>
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− | <th rowspan="2">[[130 nanometer|130 nm]]</th>
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− | <td>[[Tualatin (microprocessor)|Tualatin]]</td>
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− | <td rowspan="2">[[Pentium 4#Northwood|Northwood]]</td>
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− | </tr>
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− | <tr>
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− | <td>[[Banias (microprocessor)|Banias]]</td>
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− | <td style="background-color:white; border:none;"></td>
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− | <th style="background-color:#E6E6FF">[[Hyper-threading|NetBurst(HT)]]</th>
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− | <td style="background-color:white; border:none;"></td>
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− | <th style="background-color:#E6E6FF">NetBurst([[Multi-core processor|×2]])</th>
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− | </tr>
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− | <tr>
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− | <th rowspan="2">[[90 nanometer|90 nm]]</th>
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− | <td rowspan="2">[[Dothan (microprocessor)|Dothan]]</td>
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− | <td>[[Pentium 4#Prescott|Prescott]]</td>
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− | <td style="background-color:white; border:none;">⇨</td>
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− | <td>[[Pentium 4#Prescott 2M (Extreme Edition)|Prescott‑2M]]</td>
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− | <td style="background-color:white; border:none;">⇨</td>
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− | <td>[[Smithfield (microprocessor)|Smithfield]]</td>
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− | </tr>
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− | <tr>
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− | <td><s>[[Tejas and Jayhawk|Tejas]]</s></td>
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− | <td style="background-color:white; border:none;">→</td>
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− | <td>⇩</td>
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− | <td style="background-color:white; border:none;">→</td>
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− | <td><s>[[Tejas and Jayhawk#Design and microarchitecture|Cedarmill (Tejas)]]</s></td>
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− | </tr>
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− | <tr>
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− | <th rowspan="2">[[65 nanometer|65 nm]]</th>
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− | <td>[[Yonah (microprocessor)|Yonah]]</td>
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− | <td><s>[[NetBurst (microarchitecture)#Successor|Nehalem (NetBurst)]]</s></td>
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− | <td style="background-color:white; border:none;"></td>
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− | <td>[[Pentium 4#Cedar Mill|Cedar Mill]]</td>
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− | <td style="background-color:white; border:none;">⇨</td>
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− | <td>[[Presler (microprocessor)|Presler]]</td>
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− | </tr>
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− | <tr>
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− | <td rowspan="2"><b>Core</b></td>
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− | <td>[[Intel Core (microarchitecture)|Merom]]</td>
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− | <td colspan="6" style="text-align:left; background-color:white; border:none;">4 cores on mainstream desktop, [[DDR3]] introduced</td>
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− | </tr>
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− | <tr>
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− | <td rowspan="4"><b>Bonnell</b></td>
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− | <td rowspan="2">[[Bonnell (microarchitecture)|Bonnell]]</td>
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− | <th rowspan="2">[[45 nanometer|45 nm]]</th>
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− | <td>[[Penryn (microarchitecture)|Penryn]]</td>
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− | <td colspan="6" style="background-color:white; border:none;"></td>
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− | </tr>
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− | <tr>
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− | <td rowspan="2"><b>Nehalem</b></td>
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− | <td>[[Nehalem (microarchitecture)|Nehalem]]</td>
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− | <td colspan="6" style="text-align:left; background-color:white; border:none;">[[Hyper-threading|HT]] reintroduced, integrated [[Memory controller|MC]], PCH<br>L3-cache introduced, 256KiB L2-cache/core</td>
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− | </tr>
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− | <tr>
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− | <td rowspan="2">[[Saltwell (microarchitecture)|Saltwell]]</td>
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− | <th rowspan="2">[[32 nanometer|32 nm]]</th>
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− | <td>[[Westmere (microarchitecture)|Westmere]]</td>
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− | <td colspan="6" style="text-align:left; background-color:white; border:none;">introduced GPU on same package and [[AES-NI|AES-NI]]</td>
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− | </tr>
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− | <tr>
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− | <td rowspan="2"><b>Sandy Bridge</b></td>
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− | <td>[[Sandy Bridge]]</td>
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− | <td colspan="6" style="text-align:left; background-color:white; border:none;">on-die ring bus, no more non-[[UEFI]] motherboards</td>
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− | </tr>
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− | <tr>
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− | <td rowspan="4"><b>Silvermont</b></td>
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− | <td rowspan="2">[[Silvermont]]</td>
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− | <th rowspan="2">[[22 nanometer|22 nm]]</th>
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− | <td>[[Ivy Bridge (microarchitecture)|Ivy Bridge]]</td>
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− | <td colspan="6" style="background-color:white; border:none;"></td>
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− | </tr>
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− | <tr>
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− | <td rowspan="2"><b>Haswell</b></td>
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− | <td>[[Haswell (microarchitecture)|Haswell]]</td>
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− | <td colspan="6" style="text-align:left; background-color:white; border:none;">FIVR</td>
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− | </tr>
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− | <tr>
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− | <td rowspan="2">[[Airmont (microarchitecture)|Airmont]]</td>
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− | <th rowspan="9">[[14 nanometer|14 nm]]</th>
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− | <td>[[Broadwell (microarchitecture)|Broadwell]]</td>
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− | <td colspan="6" style="background-color:white; border:none;"></td>
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− | </tr>
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− | <tr>
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− | <td rowspan="7"><b>Skylake</b></td>
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− | <td>[[Skylake (microarchitecture)|Skylake]]</td>
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− | <td colspan="6" style="text-align:left; background-color:white; border:none;">
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− | [[DDR4]] introduced on mainstream desktop</td>
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− | </tr>
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− | <tr>
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− | <td rowspan="7"><b>Goldmont</b></td>
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− | <td rowspan="3">[[Goldmont]]</td>
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− | <td>[[Kaby Lake]]</td>
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− | <td colspan="6" style="background-color:white; border:none;"></td>
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− | </tr>
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− | <tr>
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− | <td>[[Coffee Lake]]</td>
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− | <td colspan="6" style="text-align:left; background-color:white; border:none;">6 cores on mainstream desktop</td>
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− | </tr>
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− | <tr>
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− | <td>[[Kaby Lake#Amber Lake|Amber Lake]]</td>
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− | <td colspan="6" style="background-color:white; text-align:left; border:none;">mobile-only</td>
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− | </tr>
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− | <tr>
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− | <td rowspan="4">[[Goldmont Plus]]</td>
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− | <td>[[Whiskey Lake (microprocessor)|Whiskey Lake]]</td>
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− | <td colspan="6" style="background-color:white; text-align:left; border:none;">mobile-only</td>
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− | </tr>
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− | <tr>
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− | <td>[[Coffee Lake]] Refresh</td>
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− | <td colspan="6" style="text-align:left; background-color:white; border:none;">8 cores on mainstream desktop</td>
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− | </tr>
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− | <tr>
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− | <td>[[Comet Lake (microprocessor)|Comet Lake]]</td>
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− | <td colspan="6" style="background-color:white; text-align:left; border:none;">10 cores on mainstream desktop</td>
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− | </tr>
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− | <tr>
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− | <td><b>Cypress Cove</b></td>
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− | <td>''[[Rocket Lake]]''</td>
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− | <td colspan="6" style="background-color:white; border:none; text-align:left;">Backported Sunny Cove microarchitecture for 14nm</td>
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− | </tr>
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− | <tr>
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− | <td rowspan="4"><b>Tremont</b></td>
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− | <td rowspan="2"><i>[[Tremont (microarchitecture)|Tremont]]</i></td>
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− | <th rowspan="4">[[10 nm]]</th>
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− | <td>'''Palm Cove'''</td>
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− | <td>[[Cannon Lake (microarchitecture)|Cannon Lake]]</td>
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− | <td colspan="6" style="text-align:left; background-color:white; border:none;">mobile-only</td>
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− | </tr>
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− | <tr>
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− | <td><strong>Sunny Cove</strong></td>
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− | <td>[[Ice Lake (microprocessor)|Ice Lake]]</td>
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− | <td colspan="6" style="background-color:white; text-align: left; border:none;">512KiB L2-cache/core</td>
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− | </tr>
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− | <tr>
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− | <td rowspan="2">[[Gracemont (microarchitecture)|Gracemont]]</td>
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− | <td><b>Willow Cove</b></td>
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− | <td>[[Tiger Lake (microprocessor)|Tiger Lake]]</td>
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− | <td colspan="6" style="background-color:white; border:none; text-align:left;">[[Intel Xe|X<sup>e</sup>]] graphics engine</td>
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− | </tr>
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− | <tr>
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− | <td><b>Golden Cove</b></td>
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− | <td><i>[[Alder Lake (microprocessor)|Alder Lake]]</i></td>
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− | <td colspan="6" style="background-color:white; border:none; text-align:left;">Hybrid, DDR5, PCIe 5.0</td>
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− | </tr>
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− | </table>
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− | <ul style="text-align:left;">
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− | <li><s>Strike-through</s> indicates cancelled processors
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− | <li>'''Bold names''' are microarchitectures
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− | <li>''Italic names'' are future processors
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− | </ul>
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− | }}
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− | <noinclude>{{Documentation}}</noinclude>
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